----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:49:12 09/15/2012 
-- Design Name: 
-- Module Name:    ALU_CTRL - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library WORK;
use WORK.MIPS_CONSTANT_PKG.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU_CTRL is
	port(
		ALU_Func : in std_logic_vector(5 downto 0);
		ALU_Ctrl : in std_logic_vector(1 downto 0);
		ALU_Op	: out ALU_INPUT
		);
end ALU_CTRL;

architecture Behavioral of ALU_CTRL is

	signal ALU_Op_tmp : STD_LOGIC_VECTOR(3 downto 0);

begin
--00 add 
--01 sub 
--10 alu_func
decode: process (ALU_Ctrl, ALU_Func)
begin
	if ALU_Ctrl = "00" then -- ADD
		ALU_Op_tmp	<= "0010";
	elsif ALU_Ctrl = "01" then -- SUB
		ALU_Op_tmp	<= "0110";
	else
		if ALU_Func = "100000" then
			ALU_Op_tmp	<= "0010";
		elsif ALU_Func = "100010" then
			ALU_Op_tmp	<= "0110";
		elsif ALU_Func = "100100" then
			ALU_Op_tmp	<= "0000";
		elsif ALU_Func = "100101" then
			ALU_Op_tmp	<= "0001";
		else -- "101010"
			ALU_Op_tmp	<= "0111";	
		end if;
	end if;
end process;

map_to_ALU_INPUT : process (ALU_Op_tmp)
begin
	ALU_Op.Op0 <= ALU_Op_tmp(0);
	ALU_Op.Op1 <= ALU_Op_tmp(1);
	ALU_Op.Op2 <= ALU_Op_tmp(2);
	ALU_Op.Op3 <= ALU_Op_tmp(3);
end process;
	

end Behavioral;

